APR Manager

Key Responsibilities

• Netlist-to-GDS Ownership: Lead the digital backend physical implementation from netlist to GDS, driving the complete chip sign-off and closure process.

• Full-Chip Floorplanning: Execute comprehensive full-chip floorplanning, including chip partitioning, power and ground network (PG-Mesh) design, critical module placement, utilization optimization, and pin assignment.

• Full-Flow Physical Design: Manage the overall digital backend design loop, including placement, advanced clock tree synthesis (CTS) implementation, timing closure, power calculation, IR drop analysis, Signal Integrity (SI) closure, and physical verification.

• Front-End Collaboration: Co-work closely with the front-end design team to align on logic, clock structures, and timing optimization strategies.

• Package Co-Design: Partner with the packaging team to facilitate optimized substrate design and accurate Signal Integrity/Power Integrity (SIPI) simulations.

Requirements & Qualifications

Education

• Bachelor’s degree or above in Electrical Engineering, Microelectronics, Integrated Circuits, Electronic Information, or a related technical discipline.

Professional Experience

• 5 to 8+ years of hands-on experience in digital backend (APR) design.

• A proven track record of successful tapeouts for large-scale chips using mainstream advanced process nodes (7nm, 5nm, and below preferred).

• Deep, thorough understanding of global clock distribution networks and complex structures, particularly in challenging multi-voltage domain and multi-clock environments.

• Strong familiarity with the layout, routing, floorplanning, and timing closure requirements of high-speed interface IPs (e.g., DDR5/4, PCIe Gen5/Gen4, SerDes, and HBM PHY).

• Comprehensive knowledge of formal verification, low-power design methodologies (UPF), reliability frameworks, SI, and noise reduction techniques.

Technical Skills & Tool Expertise

• EDA Tool Proficiencies: Highly adept with industry-standard sign-off and implementation tools such as Innovus, Fusion Compiler, Primetime, StarRC, Calibre, Redhawk, and equivalent platforms.

• Scripting & Automation: Strong programming and automation skills with extensive experience writing custom scripts in TCL, Python, Perl, and Shell to optimize design flows and quickly iterate.

• Problem-Solving: Unique insights into physical verification with the ability to troubleshoot complex layout/timing anomalies and independently drive engineering solutions.

Soft Skills & Language

• Excellent teamwork, interpersonal, and communication skills to integrate smoothly into a fast-paced, highly collaborative corporate culture.

• Proven ability to multi-task, manage multiple projects simultaneously, and thrive under high-pressure execution schedules.

• Good communication skills with fluent English reading and writing proficiency (fluent spoken English is a strong plus).