Chip Architect, Optical, Serdes PHY

Position Summary

We are seeking an experienced Chip Architect to define next-generation optical I/O architectures for high-bandwidth AI, HPC, and networking systems. The successful candidate will lead architecture exploration, system modeling, interface definition, and performance analysis of optical interconnect solutions integrated with ASICs and SoCs.

This role emphasizes system and chip architecture development, technology evaluation, and cross-functional technical leadership. Experience in Co-Packaged Optics (CPO), chiplets, or advanced packaging is considered a strong plus.

Key Responsibilities

Chip & System Architecture

• Define architecture for optical I/O subsystems and optical engines integrated with ASICs, AI accelerators, or networking SoCs.
• Drive architectural tradeoff studies covering bandwidth, latency, power efficiency, scalability, reliability, and cost.
• Develop system-level models and simulations to evaluate optical interconnect performance.
• Define interfaces, protocols, and architectural requirements for next-generation high-bandwidth interconnects.
• Collaborate with ASIC, PHY, photonics, packaging, and system teams to align architecture with product requirements and technology roadmaps.

Optical Communication Architecture

• Define end-to-end optical link architecture and system specifications.
• Perform link budget analysis, performance modeling, and architecture feasibility studies.
• Analyze optical and electrical impairments and identify architectural approaches for performance optimization.
• Evaluate modulation schemes, coding methods, and signal processing techniques applicable to optical interconnect systems.

High-Speed PHY Architecture

• Define architectural requirements for high-speed electrical and optical PHYs.
• Guide system-level design considerations involving SerDes, PAM4 signaling, equalization, clock recovery, and link management.
• Establish PHY performance targets and interface specifications required to achieve overall system objectives.

Technology Exploration & Innovation

• Evaluate emerging technologies for optical I/O, chiplet interconnects, and heterogeneous integration.
• Develop proof-of-concept models and prototypes to validate new architectural concepts.
• Drive innovation in optical connectivity solutions for future AI and HPC platforms.
• Contribute to technology strategy and long-term architectural roadmap development.

Required Qualifications

Education

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, Photonics, or related disciplines.

Technical Expertise

• Strong experience in chip architecture, system architecture, or interconnect architecture development.
• Deep understanding of high-speed communication systems and optical interconnect technologies.
• Experience with system-level modeling and performance analysis.
• Knowledge of high-speed SerDes architectures and modern PHY technologies.
• Familiarity with multi-lane interfaces and high-bandwidth networking systems.
• Experience defining technical requirements and architecture specifications for complex semiconductor products.

Modeling & Analysis

• Experience using architecture and simulation tools such as:
  • MATLAB / Simulink
  • SystemVerilog or equivalent modeling environments
  • Signal integrity and communication system analysis tools
• Ability to evaluate architectural tradeoffs using quantitative modeling methodologies.

Leadership & Collaboration

• Proven ability to lead cross-functional technical discussions and architecture reviews.
• Strong written and verbal communication skills.
• Ability to influence technical direction across multiple engineering disciplines.