28 Technical, Operations & Engineering jobs in Taipei, Hsinchu

Job Description – Business Development Manager (Semiconductor Packaging) Role Overview This role focuses on engagement with fabless semiconductor companies , particularly in Advanced Packaging and Automotive Packaging . The ideal candidate must bring hands-on semiconductor packaging experience (tradit...

Responsibilities Provide technical support for key customers, both remotely and onsite, to win and maintain accounts. Assist in the design-in process by solving acoustic and electrical issues, answering product-related questions, reviewing hardware, and performing hands-on debugging. ...

Serdes/AIP/IO layout Over 6 months of Layout experience in 28nm/22nm process nodes. Experience in FinFET Process Layout is a plus. Hands-on experience with Physical Verification (DRC/LVS/ERC/ANT/PERC). Layout experience with Analog IP, high-speed SerDes PHY, and DDRIO is a plus. Familiar with...

工作内容:  1.獨立負責專案 PCB Layout 的 PlacementㆍRouting與Gerber輸出  2.協助解決產品開發階段PCB廠與PCA廠的生產問題  3.執行專案的 Placement 走評估  其他條件:  1.熟悉Allegro 17.4以上版本操作  2.具備3-5年以上PCBLayout 經驗  3.熟悉電子產品/PC類產業專業知識,有高速訊號布線經驗佳  4.具備電腦/筆電PCBLayout經驗,能獨立完成專案者優先  5.有四層板以上、pin數達10,000+Layout經驗者優先  6...

Key Responsibilities: Define block-level micro-architecture and develop detailed design specifications. Implement RTL designs while optimizing for power, area, and timing constraints. Collaborate with the Verification team to ensure functional correctness. Work closely with the Backend team t...

Primarily tasked with verifying system-level design Create test plans, test platforms, test cases, reference models, coverage models, and regression suites Conduct RTL simulation, function verification, and fault debugging Lead efforts to attain coverage closure Preferably experienced with ARM-base...

1. Qt C++ for Simulation GUI 2. Write compiler and Parser for verilog and system verilog 3. Optimization for software architecture. 4. Responsible for designing, developing, and debugging on verification EDA (electronic design automation) tool for ESL/RTL SoC design. ======== Qualification ======== ...