Physical Design Engineer
發佈於： 8/7/2026
Kowloon 香港
Permanent
半導體
Job Description for Senior Engineer/Principal Engineer
(1) Familiar with Cadence tool INNVOUS or SNPS Fusion Compiler is essential.
(2) Familiar with part of top-level job experiences is essential.
(3) Familiar with front end/middle-end flow especially have experience with synthesis/SDC
analysis.
(4) Perform full chip power analysis, physical validation and STA.
(5) Have deep analysis and debugging experiences for design.
(6) Have big/advance chip project backend experiences.
(7) Good communication skills with colleagues and customers are essential.
(8) Efficient teamwork and collaboration awareness is needed.
(9) Mandarin is preferrable.
(1) Familiar with Cadence tool INNVOUS or SNPS Fusion Compiler is essential.
(2) Familiar with part of top-level job experiences is essential.
(3) Familiar with front end/middle-end flow especially have experience with synthesis/SDC
analysis.
(4) Perform full chip power analysis, physical validation and STA.
(5) Have deep analysis and debugging experiences for design.
(6) Have big/advance chip project backend experiences.
(7) Good communication skills with colleagues and customers are essential.
(8) Efficient teamwork and collaboration awareness is needed.
(9) Mandarin is preferrable.