【先進製程】Senior APR Engineer_台北/新竹

【先進製程】Senior APR Engineer_台北/新竹

Responsibilities 

• Lead full Netlist-to-GDSII implementation flow, including Floorplan, Placement, CTS, Routing, and Physical Optimization.  

• Drive timing closure, IR/EM analysis, DRC/LVS sign-off, and tape-out readiness.  

• Resolve advanced node challenges on N7/N5/N3 technologies, including FinFET, LDE, and Multi-patterning issues.  

• Implement low-power design methodologies using UPF/CPF, multi-voltage domains, and power gating.  

• Develop Tcl/Python automation scripts to improve design productivity and PPA.  

Requirements 

• M.S. in EE, CS, or related field.  

• 10+ years of APR / Physical Design experience with successful N7/N5/N3 tape-out(s).  

• Strong hands-on experience with Innovus or ICC2/Fusion Compiler.  

• Proficient in PrimeTime/Tempus, Voltus/RedHawk, and Calibre.  

• Solid understanding of MMMC, POCV/LVF, Signal Integrity, IR Drop, and EM analysis.  

Preferred 

• Experience with CoWoS, InFO, 2.5D/3D IC packaging.  

• Familiarity with PCIe Gen5/Gen6 and DDR5 implementation.  

• Experience handling large-scale SoC designs (>10M gates).