Sr. to Lead Test Hardware Engineer
Publiée le : 06-11-26
Taipei City Northern Taiwan Taïwan
CDI
Semiconductor
Job Description
We are looking for experienced Test Hardware Engineers, ranging from Senior Engineer to Lead level, to support test hardware development, bring-up, debugging, and correlation activities in a high-volume semiconductor manufacturing environment.
The successful candidate will play a key role in ensuring test hardware reliability, production stability, and yield improvement across wafer sort and final test operations.
Key Responsibilities
1. Test Hardware Bring-up & Qualification
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Support load board and probe card bring-up for new products on the Advantest V93K platform.
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Perform hardware validation, checkout, and debugging during silicon bring-up.
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Conduct GR&R, stability, and repeatability evaluations before production release.
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Collaborate with Test Engineering and Design teams throughout NPI and HVM transitions.
2. Hardware Debug & Failure Analysis
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Troubleshoot production issues related to test hardware, interfaces, and signal integrity.
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Perform bench-to-ATE correlation and root cause analysis using laboratory equipment such as oscilloscopes, DMMs, and thermal tools.
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Identify and resolve issues involving sockets, load boards, pogo pins, probe cards, and contact failures.
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Support RMA investigations, yield excursions, and lot-on-hold analysis.
3. Test Correlation & Production Release
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Perform ATE-to-ATE, ATE-to-bench, and load board-to-load board correlation.
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Prepare correlation reports and define acceptance criteria for production readiness.
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Validate test limits, guard bands, and parametric consistency across multiple test sites.
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Support hardware qualification and release to OSAT and production sites.
4. Production Support & Yield Improvement
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Monitor hardware-related yield performance and drive root cause investigations and corrective actions.
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Analyze failure trends, bin distributions, and contact yield issues.
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Support test time reduction (TTR) and production throughput optimization.
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Work closely with Product Engineering teams to improve yield and production efficiency.
5. Hardware Design & Optimization
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Review load board schematics, PCB layouts, and signal integrity considerations.
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Optimize site configurations, signal integrity, power distribution, and thermal performance.
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Support multi-site scalability and hardware cost optimization.
6. Cross-functional Collaboration
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Work closely with Test Engineering, Product Engineering, Failure Analysis, OSAT, and Manufacturing teams.
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Share technical knowledge and best practices in hardware debugging and correlation.
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For Lead-level candidates, provide technical guidance to junior engineers and drive project execution, risk management, and stakeholder communication.
Requirements
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Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
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2+ years of experience in semiconductor test engineering or test hardware engineering.
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Hands-on experience with Advantest V93K platforms (SmarTest 7/8).
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Experience in load board and/or probe card bring-up, validation, and debugging.
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Understanding of semiconductor production testing, including wafer sort (WS) and final test (FT).
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Knowledge of silicon bring-up, characterization, test correlation, and hardware troubleshooting.
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Understanding of signal integrity, power delivery, and analog/digital measurements.
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Familiarity with ATE instrumentation such as DPS, AVI, PPMU, and HSIO.
Preferred Qualifications
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Experience supporting high-volume manufacturing (HVM).
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Familiarity with data analysis tools such as JMP, Exensio, or Excel.
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Understanding of test program structure and hardware interactions.
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Exposure to JEDEC / AEC qualification and reliability testing.
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Experience working with global engineering teams and OSAT partners.
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Strong problem-solving, communication, and cross-functional collaboration skills.