Dry Etch Process, Engineer to Manager

• Lead the development, characterization, and optimization of advanced Dry Etch processes for cutting-edge memory structures.

• Collaborate cross-functionally with integration, metrology, equipment, and R&D teams to ensure process robustness and manufacturability.

• Define and execute technical roadmaps aligned with advanced memory scaling requirements and yield improvement goals.

• Evaluate and implement next-generation etch technologies, novel chemistries, and advanced hardware platforms.

• Mentor and guide junior engineers, fostering a culture of innovation and technical excellence.

• Interface with strategic equipment vendors and global partners to co-develop innovative solutions.

• Drive root cause analysis and continuous improvement initiatives for complex, process-related yield limiters.

• Present technical findings, strategic roadmaps, and project recommendations to executive leadership and global teams.

Qualifications:

• Ph.D. or Master’s degree in Electrical Engineering, Materials Science, Chemical Engineering, Physics, or a related discipline.

• Hands-on experience in Dry Etch process development, with a strong preference for background in DRAM or advanced memory technologies.

• Proven track record of technical leadership and project ownership in semiconductor process engineering.

• Deep understanding of plasma etch mechanisms, advanced process control, and defect mitigation strategies.

• Extensive experience with industry-standard advanced etch tools (e.g., Lam Research, TEL, AMAT) and complex characterization techniques.

• Strong analytical, problem-solving, and cross-cultural communication skills.

• Demonstrated ability to lead cross-functional teams and manage complex, multi-site projects.

Preferred Skills:

• Specialized experience with high aspect ratio etching, critical dimension (CD) control, and selectivity challenges in advanced memory nodes.

• Familiarity with advanced data analytics, Design of Experiments (DOE) methodologies, and Statistical Process Control (SPC) tools.

• Comprehensive knowledge of integration challenges in sub-20nm memory technology nodes.