57 研發、技術、營運和工程 職務 台灣

【新北｜Server Hardware Engineer｜大型科技製造集團】 知名大型科技製造集團持續擴大 Server 團隊，現招募具備 Server Hardware Development 經驗的工程人才，參與新世代 Server、AI Server 及高效能運算平台的開發。 職務內容： • 負責 Server Hardware Architecture、Circuit Design 及 Hardware Debug • 參與 Server Platform 從 EVT、DVT、PVT 至 MP 的完整開發流程 • 進行硬體設計、驗證及問題分析，確保產品開發進度與品質 • 與 BI...

Position Overview We are seeking an exceptional and forward-thinking Staff Electrical Engineer to join our extraordinary team in Taipei, Taiwan. In this pivotal role, you will be directly accountable for pioneering the technology and platforms for our next-generation high-power supplies. Your mission ...

Basic Information Reason for Hiring: Business expansion Travel Requirements: Required (US, approx. 3 times/year) Fluent in English Personality Traits Required Strong interpersonal skills; comfortable interacting with overseas clients Required Experience ...

工作內容 聚焦 Server / AI Server / High-Performance Computing 負責 Signal Integrity / Power Integrity 技術分析與問題解決 涵蓋高速介面、PCB、Power Delivery Network、Simulation & Validation 與 HW、Layout、Mechanical、Thermal、Manufacturing 等團隊跨部門合作 擔任 Technical Leader ，主導技術方向、Methodology 與 Design Guideline 參與下一世...

Key Responsibilities Strategic Customer Alignment & Business Growth Drive Strategic Growth: Lead high-impact projects to secure new business, build lasting customer trust, and coordinate regular executive management reviews. Map Technology Inflections: Engage deeply with customers...

System Applications Engineer｜系統應用工程師 Job Responsibilities 1. Customer & Sales Technical Support Partner with Sales and FAE teams to support design wins and build strong relationships with key customers and partners. Provide software integration, debugging, and technical support for Tier-1 ...

產品硬體平台開發 ：主導智慧手持設備、邊緣 AI 裝置、物聯網（IoT）、航太電子及電動車等產品之硬體系統規劃與設計，研發鏈全程參與至量產落庫。 系統整合與架構驗證 ：統籌電路設計、射頻（RF）、光學影像及觸控顯示等核心模組之系統化整合，主導硬體 Debug、性能測試與整體功能調校。 關鍵零組件選型與技術審評 ：評估與引進關鍵元件（如 Sensors、Camera Module、RF 通訊模組及顯示面板等），確立技術規格並兼顧產品效能與成本品質。 試量產推動與品質優化 ：串聯製造單位（NPI/Factory）順暢推進試產作業，掌握產線異常分析，提...

Key Responsibilities Develop, maintain, and enhance automated static timing analysis (STA) and timing closure methodologies using industry-standard signoff tools such as PrimeTime, PrimeClosure, and Tempus. Drive timing convergence across the implementation flow by establishing strong correlation betw...

Key Responsibilities Develop and deploy AI-assisted implementation methodologies using Cadence Cerebrus to enhance design productivity and QoR. Integrate Cerebrus with RTL synthesis and physical implementation flows, enabling automated design space exploration and optimization. Analyze implementat...

Key Responsibilities Architect, develop, and continuously enhance RTL-to-gate synthesis methodologies with a strong focus on physical-aware implementation using Cadence Genus. Partner with front-end and back-end design teams to deploy synthesis best practices, provide technical consultation, and drive...