Senior IC Advanced Packaging Engineer

Key Responsibilities

• Technical Authority: Act as the lead expert for IC and System-in-Package (SiP) solutions, guiding multiple products and programs through the full development lifecycle.

• Roadmap Ownership: Define and own the package architecture and technology roadmap, ensuring alignment with product performance, cost efficiency, and long-term scalability.

• Chiplet Strategy: Spearhead chiplet-based packaging initiatives, incorporating UCIe, silicon interposers, and advanced Redistribution Layer (RDL) strategies.

• Design & Layout: Lead hands-on package design and physical layout for critical structures, including high-speed SerDes/PHY (PCIe, CXL), LPDDR5, and other multi-gigabit interfaces.

• Advanced Standards: Define substrate stack-ups, material selection, bump/RDL architectures, and DFM guidelines tailored for advanced process nodes.

• Cross-Functional Optimization: Drive critical trade-offs between Signal Integrity/Power Integrity (SI/PI), thermal management, mechanical stability, and reliability.

• Supply Chain Leadership: Lead technical engagements with OSATs, foundries, and key substrate suppliers to ensure manufacturing readiness and technology co-development.

• Strategic Influence: Advise on product roadmaps, risk mitigation, and investment decisions through deep technical insight.

• Methodology Development: Establish scalable design methodologies, best practices, and reusable packaging flows to enhance team productivity.

Qualifications & Requirements

• Education: BSEE or MSEE in Electrical Engineering or a related field (PhD preferred).

• Experience: 10+ years of extensive IC packaging expertise specifically for SoCs, ASICs, or high-performance memory products.

• Communication: Must be fluent in English with the ability to lead technical discussions and influence global stakeholders.

• Technical Depth: Deep hands-on expertise in Flip-Chip BGA (FCBGA), SiP, RDL, silicon interposers, and UCIe chiplet architectures.

• Design Acumen: Strong command of electrical, mechanical, thermal, and reliability trade-offs, alongside advanced packaging materials and DFM/yield optimization.

• Leadership: Proven ability to operate autonomously and make high-impact decisions within a fast-paced, high-growth environment.

Required Technical Background

• End-to-End Delivery: Technical leadership of multiple packaging programs from early-stage architecture through to high-volume production.

• High-Speed Interfaces: Demonstrated experience with high-speed SerDes package development (PCIe Gen5, LPDDR5/LPDDR5X, USB 3.x, or 10G+ interfaces).

• Architecture: Proven track record in defining die-to-die and chiplet-based RDL/bump architectures.

• Vendor Management: Direct history of collaboration with OSATs and foundries for technology ramp-up.

• Team Synergy: Strong cross-functional leadership across design, product, test, operations, and reliability teams.

Preferred Tools & Skills

• EDA Tools: Expert-level proficiency in Cadence Allegro Package Designer (APD) or equivalent EDA platforms.

• Simulation: SI/PI expertise, including S-parameter extraction and PDN optimization using HFSS, SIwave, or Ansys Designer.

• Platform Building: Experience building new packaging methodologies or platforms from the ground up.