Fundamental IP Design Kit and Characterization Man

Job Overview

We are seeking an experienced engineering leader to drive the development, characterization, modeling, validation, and design kit delivery of advanced semiconductor IP solutions, including Standard Cell Libraries, Memory IP, and I/O IP, for leading-edge CMOS and FinFET technologies. This role will provide both technical and project leadership while partnering with global engineering teams to develop methodologies, automation flows, and design enablement solutions supporting complex ASIC and SoC products.

Key Responsibilities

• Lead the development and delivery of Standard Cell, Memory, and I/O IP across advanced process technologies.
• Drive design kit delivery, including behavioral, timing, power, and variation models for design implementation and sign-off.
• Oversee IP characterization activities and ensure high-quality library releases across multiple technology nodes.
• Lead RTL and behavioral model development using Verilog/SystemVerilog and establish comprehensive verification methodologies.
• Develop and enhance characterization and EDA automation flows using Python, Perl, and TCL.
• Collaborate with foundries, EDA vendors, and internal design teams to improve design methodologies and tool flows.
• Support ASIC and SoC development teams throughout the design lifecycle, including debugging and root-cause analysis.
• Drive cross-functional projects involving silicon design, verification, implementation, and product engineering teams.
• Mentor engineers, provide technical guidance, and lead project execution across geographically distributed teams.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Solid understanding of Standard Cell, Memory, or I/O development, characterization methodologies, and design kit generation.
• 6+ years of experience in ASIC, SoC, IP, library development, characterization, timing analysis, or related semiconductor disciplines.
• Strong knowledge of CMOS, FinFET, transistor operation, digital circuit design, and optimization techniques.
• Experience with design kit delivery, IP characterization, and library validation.
• Hands-on experience with Liberty formats (NLDM, CCS, LVF), statistical variation analysis, and timing model generation.
• Proficient in Python, Perl, or TCL within Linux/UNIX environments.
• Familiarity with RTL design, SystemVerilog, DFT, BIST, STA, and Spice-based validation methodologies.
• Strong debugging, analytical, and problem-solving skills.
• Excellent communication skills with experience working across multidisciplinary engineering teams.

Preferred Qualifications

• 8+ years of semiconductor industry experience.
• Experience leading technical projects or engineering teams.
• Background in library characterization, memory compiler development, custom IP development, or EDA methodology development.
• Experience collaborating with foundries, EDA vendors, and distributed global teams.
• Prior experience managing engineers, mentoring team members, and driving project execution from concept through production release.