DV Talent (Oversea BU Leader)

This position provides a strong career path toward a DV Team Lead/Manager role, with opportunities to mentor and manage international Design Verification engineers and drive collaboration across global engineering teams.

Responsibilities:

• Lead system-level design verification activities for complex SoC/IP products.
• Define and develop comprehensive verification strategies, including test plans, verification environments, test cases, reference models, coverage models, and regression suites.
• Perform RTL simulation, functional verification, root-cause analysis, and debug of design issues.
• Drive verification execution and achieve functional/code coverage closure.
• Collaborate closely with design, architecture, and software teams to ensure product quality and timely project delivery.
• Continuously improve verification methodologies, automation flows, and verification efficiency.

Preferred Qualifications:

• Familiarity with ARM or RISC-V architectures and AMBA bus protocols.
• Experience with SystemVerilog Assertions (SVA) and UVM-based verification environments.
• Strong debugging, problem-solving, and communication skills.