Manufacturing Director (Foundry & OSAT Management)

Position Overview

Reporting directly to the Executive Management (Head of Operations / General Manager), the Head of Global Quality will oversee and strategize the comprehensive Quality Management System (QMS) for our global product portfolio, encompassing IoT Memory, AI/HPC High-Bandwidth Memory, and 3D Stacked Memory architectures.

This executive role demands a robust Fabless quality governance mindset. The ideal candidate will orchestrate end-to-end quality defense, specializing in New Product Introduction (NPI) quality gating, outsourced supply chain quality engineering (Foundry & OSAT), rigorous change control, and the management of strategic relationships and complaint resolution with global Tier-1 clients (e.g., top-tier AI chip makers, hyperscalers, and system OEMs).

Key Responsibilities

1. Global Outsourced Supply Chain Quality Governance (Foundry & OSAT)

• Outsourced Quality Framework: Act as the executive technical window to leading foundries and OSAT partners; define, enforce, and optimize comprehensive outsourced Quality Control Plans.

• Excursion & Crisis Management: Spearhead the containment and resolution of major manufacturing or test excursions; drive cross-functional Root Cause Analysis (RCA) leveraging 8D methodologies, Fishbone, and 5-Whys.

• Process Change Control: Oversee risk assessments and validation strategies for foundry and assembly process changes (PCN/PCR), safeguarding existing product yields and field reliability against unauthorized or unvetted modifications.

2. New Product Introduction (NPI) & Design Quality Assurance

• Preventative Design Quality: Engage early in the product lifecycle (Design-in to Tape-out); collaborate with R&D and PM teams to implement proactive quality controls through robust DFMEA and PFMEA execution.

• Reliability Qualification: Architect and execute product qualification plans in compliance with global standards (JEDEC, AEC-Q100, etc.), ensuring memory products achieve elite high-temperature operating life (HTOL), endurance, and structural package reliability.

3. Elite Customer Quality Engineering (CQE) & Client Relations

• Tier-1 Account Interface: Serve as the company's highest technical spokesperson for quality; host international client audits and lead technical alignments with global tech giants, network infrastructure leaders, and AI server clients.

• RMA & Customer Complaint Architecture: Optimize and streamline the Return Merchandise Authorization (RMA) workflow, ensuring precision in Failure Analysis (FA) turn-around time and crisp 8D reporting to enhance international client trust.

4. QMS Optimization & Laboratory Governance

• System Evolution: Champion Total Quality Management (TQM) principles across the organization; maintain and audit ISO 9001 frameworks while strategically positioning the company for automotive-grade systems integration (e.g., IATF 16949).

• FA Lab Management: Govern the internal Failure Analysis (FA) and inspection laboratory, overseeing capital equipment procurement, Standard Operating Procedure (SOP) design, and Environmental Health and Safety (EHS) compliance.

• Executive Quality KPI Metrics: Establish, track, and analyze enterprise-level metrics (e.g., dppm, RMA rates, supplier yield curves); deliver high-impact quality governance reports to the CEO and General Manager regularly.

Requirements & Qualifications

• Educational Background: Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Materials Science, Chemical Engineering, Industrial Engineering, or a related STEM field.

• Professional Experience:

  • Minimum of 12 years of progressive semiconductor experience, with at least 10 years in a dedicated quality management leadership role (Manager, Director, or equivalent).

  • Highly preferred: Proven track record in an IC Design House (Fabless) environment or a prominent Memory IDM / Fabless enterprise.

• Core Competencies:

  • Proficient knowledge of semiconductor device physics, wafer fabrication, and advanced memory architectures (DRAM, PSRAM, Flash) across wafer sort (CP) and final test (FT) processes.

  • Expert-level command over Failure Analysis (FA) methodologies, JEDEC reliability testing standards, Statistical Process Control (SPC), FMEA, and Six Sigma data-driven diagnostics.

  • Hands-on exposure to automotive semiconductor quality standards (IATF 16949, AEC-Q100) is highly advantageous.

• Soft Skills & Language Proficiencies:

  • Business English: Exceptional communication, negotiation, and technical presentation skills in English, with a proven ability to interface independently with global Tier-1 executive clientele.

  • Leadership & Crisis Management: High Emotional Intelligence (EQ) with a demonstrated ability to steer cross-functional alignments (R&D, Sales, Operations) and resolve high-pressure supply chain or customer crises.
    
    
     

    Matt Hsu Deputy Director

    +886 2 7750 5717 | +886 912 816 131     Matt.Hsu@morganphilips.com   tw.morganphilips.com   Let's connect on LinkedIn             32F, No.333, Sec. 1, Keelung Rd., Xinyi District, Taipei 台北市信義區基隆路一段333號32樓3209室