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MAKING SUCCESS STORIES HAPPEN
 

We are seeking an executive-level Senior Director of Packaging Technology to establish and drive the strategic vision, architecture, and deployment of advanced semiconductor packaging solutions. Reporting to executive leadership, this role will direct global engineering teams in bringing high-performance analog, power, and multi-chip integration products from concept through qualification into high-volume manufacturing (HVM).

This is a high-visibility leadership position responsible for setting multi-year packaging roadmaps, driving substrate and vendor strategies, and solving complex Chip-Package Interaction (CPI) challenges to support sustainable business growth.

Key Responsibilities

Strategic Leadership & Organizational Growth

  • Global Team Leadership: Lead, scale, and mentor high-performing global engineering teams across package design, assembly, thermal/mechanical modeling, and reliability.

  • Technology & Capacity Roadmaps: Partner with corporate leadership to define multi-year capability, technology, and footprint roadmaps aligned with business growth, capital expenditure, and resource allocation.

  • Supply Chain & Vendor Strategy: Manage key technical and strategic relationships with OSATs, substrate suppliers, assembly partners, and material vendors to ensure supply chain resilience, technology readiness, and cost optimization.

Package Architecture & Technology Development

  • End-to-End Technology Selection: Define and deploy package architectures based on strict electrical, thermal, mechanical, reliability, and cost constraints across advanced platforms, including:

    • Advanced Packaging: Flip-Chip, Wafer-Level Packaging (WLP / FOWLP), Panel-Level Packaging (PLP).

    • Heterogeneous Integration: System-in-Package (SiP), Multi-Chip Modules (MCM), and Power Modules.

    • Power Applications: High-power leaded and embedded die architectures.

  • Chip-Package Interaction (CPI): Oversee package layout reviews, substrate stack-up definitions, interconnect strategies, and material selections while managing CPI stresses and design trade-offs.

  • Simulation & DFM Leadership: Drive advanced thermal, mechanical, and electrical modeling alongside Design for Manufacturability (DFM) guidelines to ensure first-pass success.

NPI Execution, Qualification & Yield Enhancement

  • Assembly Process & NPI: Develop assembly flows and process specifications for internal captive facilities and external OSAT partners from NPI prototype builds through volume ramp.

  • Qualification & Reliability: Oversee package qualification strategies, including Design of Experiments (DOE), stress testing, and reliability standard compliance.

  • Failure Analysis & Issue Resolution: Drive rapid-response root cause analysis (RCA) and corrective action implementation for complex packaging failures during qualification and high-volume production ramps.

  • Standardization: Establish and maintain global design rules, package specifications, process documentation, and intellectual property.

Key Qualifications & Leadership Experience

Experience & Education:

  • Education: M.S. or Ph.D. in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or a related technical discipline.

  • Industry Experience: 15+ years of hands-on experience in semiconductor packaging or advanced microelectronics packaging, with a proven track record in analog and power products.

  • Leadership Experience: 10+ years in executive/global engineering management with demonstrated success leading cross-functional, multi-site teams.

Technical & Strategic Competencies:

  • Ecosystem Expertise: Deep, hands-on knowledge of OSAT operations, substrate manufacturing, raw material ecosystems, and semiconductor supply chain dynamics.

  • Advanced Mechanics & Physics: Solid foundation in thermal/mechanical stress modeling, power dissipation, and CPI dynamics.

  • Quality & Reliability: Thorough understanding of industry qualification standards (e.g., JEDEC/AEC), DOE methodology, and advanced failure analysis techniques.

  • Executive Presence: Outstanding cross-functional communication, strategic negotiation, and stakeholder management skills.

立即申請: Sr. Director, Semiconductor Package
參考編號: GC878359

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Sr. Director, Semiconductor Package
Hsinchu, Northern Taiwan | Permanent
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