CAD Flow Engineer (STA/Timing)

Key Responsibilities

• Develop, maintain, and enhance automated static timing analysis (STA) and timing closure methodologies using industry-standard signoff tools such as PrimeTime, PrimeClosure, and Tempus.
• Drive timing convergence across the implementation flow by establishing strong correlation between synthesis, APR, and signoff environments, reducing iteration cycles and improving design predictability.
• Partner with frontend and backend engineering teams to define timing signoff strategies, constraint management methodologies, ECO guidelines, and best practices for advanced-node designs.
• Build and maintain automation frameworks for timing analysis, report generation, constraint validation, and ECO implementation to improve engineering efficiency and shorten turnaround time.
• Identify timing bottlenecks, root causes, and optimization opportunities, providing methodology guidance to accelerate timing closure across multiple projects.

Requirements

• Proven experience in CAD/EDA methodology development or timing signoff engineering with a strong focus on STA and timing closure.
• Solid hands-on expertise with industry-standard STA tools, including Synopsys PrimeTime and Cadence Tempus, in advanced process technologies.
• Strong understanding of timing constraints (SDC), timing variation methodologies (OCV/AOCV/POCV), SI/noise analysis, crosstalk effects, and physical-aware ECO optimization flows.
• Proficiency in Linux environments and scripting languages such as Tcl, Python, and Perl for flow automation and infrastructure development.
• Strong communication and collaboration skills to support cross-functional engineering teams and drive timing closure methodologies across projects.

Preferred Qualifications

• Experience developing enterprise-level timing signoff infrastructure and CAD flows.
• Familiarity with ML/AI-assisted timing optimization, design automation, or intelligent EDA workflows.
• Knowledge of advanced-node implementation challenges, including MCMM timing analysis and large-scale SoC design methodologies.